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Circuit Modeling

Circuit modeling is a natural extension of single device modeling. With IC-CAP's flexible structure, it is as easy to measure and characterize a multicomponent circuit as a single device. This section provides details for performing circuit modeling; typical applications are also provided to use as a guide for meeting specific circuit modeling requirements.

Definition of an IC-CAP Circuit

IC-CAP defines a circuit as any connection of two or more components. Previous sections have dealt primarily with single devices such as bipolar, GaAs or MOS transistors. An IC-CAP circuit can be a simple two-resistor voltage divider or a complex operational amplifier or A/D converter.

The circuit, like a single device, is specified in the Circuit folder of the model window using SPICE compatible circuit definition syntax. All circuit decks in IC-CAP begin with the .SUBCKT subcircuit definition and end with the .ENDS statement. Circuit modeling allows more accurate solutions to many single device modeling requirements and expands the level of systems modeling possible.

IC-CAP Circuit Modeling Operations

With IC-CAP, every type of characterization operation performed on a single component can also be performed on a circuit. IC-CAP allows easy measurement of circuit characteristics, extraction and optimization of model parameters, and simulation of the circuit's performance. Measurement and simulation operations use the same setup information as single components. Extraction and optimization operations enable more options for methods of obtaining model parameters. These operations can be performed on the circuit as a whole or on any sub-component of the circuit. This is explained in the section, Circuit Parameter Extraction.

Defining a Circuit

The process of defining a circuit in IC-CAP is similar to defining a single device. The main difference is the interconnection of the components and the use of subcircuit lines to define the circuit block. For detailed information on defining circuits, refer to SPICE Simulators, SPECTRE Simulator, or Saber Simulator).

Supported Circuit Components

Circuits in IC-CAP support the standard components that can be simulated with SPICE:

Passive elements  R, L, C, Transmission lines
Semiconductors  Bipolar, MOS, GaAs, JFET, Diode
Sources  V, I, VCVS, VCIS, ICVS, ICIS

The syntax for defining a circuit in IC-CAP is similar to a SPICE simulation input deck. Each line contains a component, its node numbers, value, and (if applicable) an associated model name reference. Proper specification and use of these components is critical to the success of circuit simulation and parameter extraction.

In general, independent voltage sources are specified as inputs within a given setup. This allows you to specify their values and use them in additional numerical or graphic analysis. Some of the differences between SPICE and IC-CAP circuit definitions are listed.

  • The .OPTIONS statement (if used) must be the first line in the circuit description. All options must be on one line (no continuation).
  • The next line of the circuit is .SUBCKT.
  • A TITLE specification is automatically generated by IC-CAP and should not be included in the circuit definition.
  • The last line of the circuit is .ENDS
  • An .END statement is automatically generated by IC-CAP and should not be included in the circuit definition.

The following figure shows an example circuit description. This circuit defines the input section of an ECL OR/NOR logic gate. (ECL OR/NOR Schematic Diagram shows the schematic.) This circuit is referenced several times in this section. You can create it using the circuit editor or read it from the file $ICCAP_ROOT/data/ECLornor.mdl.

Circuit Description for an ECL OR/NOR Logic Gate

When you enter the circuit description in the Circuit folder of the model window, moving the mouse out of the Circuit folder automatically causes the circuit to be parsed, that is, the specified circuit elements are read and entries are created for them in Model Parameters. When they are added initially, they assume the value specified in the circuit description. To change a value subsequently, you must change it in Model Parameters. To change all entries in Model Parameters to the values in the circuit description, choose Reset.

Note the difference in the Parameters table parameter names for a transistor in a circuit. In a single transistor circuit, the model parameter names of the transistor are the entries in the Parameters table. In a multi-component circuit the transistor's model parameters must be associated with a specific model, so the parameters take on a prefix of that model's name. Thus, the forward Beta model parameter BF for a model named NPN1 is listed in the Parameter Editor as NPN1.BF. In the example above, transistors Q1 and Q2 both use the NPN1 model, while transistor Q0 uses the NPN2 model.

Circuit Measurement

The process of measuring a circuit in IC-CAP is identical to measuring a single device. The circuit stimuli and responses are specified in the input and output tables, respectively, of the Measure/Simulate folder. You can perform a measurement by clicking Measure in the Measure/Simulate folder the DUT or Setup levels. In performing measurements on circuits, there are several additional items not found in single component measurement.

Multiple Instrument Names

In measuring a single component, it is common to use only one DC source and measurement instrument because only four terminals are involved. The typical circuit can have more than four terminals and require several DC source and measurement instruments. Any number of instruments of the same or similar type can be connected to the circuit under test as long as they are entered in Hardware Setup. When using multiple instruments, each of their units must have a unique name.

Isolating Circuit Elements for Measurement and Extraction

The characterization of a circuit may require the measurement and modeling of several sub-circuit elements. The accuracy of the sub-circuit model generated is dependent upon how well that circuitry can be isolated from the rest of the overall circuit.

Examine the simplified schematic of the input to an ECL OR/NOR gate in the following figure. The input stage of this circuit is a differential amplifier with a collector resistor in each leg and a resistor for a current source. It is possible to characterize the individual transistors in this circuit by selectively biasing only the terminals that make it active and that keep other parts of the circuit in an off or latent state. In this case, biasing IN1, VCC, and VEE turns on the circuit that contains RL1, Q1, and RIEE. These components have now been isolated so that their model parameters can be extracted. This type of selective measurement allows characterization of individual or small groups of sub-circuit elements.

ECL OR/NOR Schematic Diagram

Circuit Parameter Extraction

Circuit parameter extraction is identical to single component parameter extraction through the use of Transforms. However, because circuits are custom in nature, most of the extraction routines must also be custom designed. With the availability of the Program function and optimize transforms, this is simple and quick to evaluate and execute. The critical factor in a successful circuit level parameter extraction is the ability to make a measurement and subsequent extraction involving only the dominant component parameters.

For a full model extraction of a single component, you will attain more accuracy if that device is available without any additional components connected to it. For most functional block level circuits however, a subset of the transistor model parameters is usually sufficient for studying circuit behavior.

Extracting Transistor Parameters Using Library Functions

In the explanation of a selective measurement on a sub-portion of a circuit in the previous section, Q1 and its neighboring resistors were isolated in the ECL logic gate. The forward active model parameters can be extracted from this measurement using the model extraction functions in the function list or by setting up a custom optimization. To access the functions, add transforms that use them to a setup that contains the measurement. It is possible to use the provided transistor extraction functions to obtain model parameters for devices connected into a larger circuit.

Because all models in a circuit have model parameters in the Parameters table with the model's name as a prefix, IC-CAP must be told which model to use with the extraction transforms. This is easily done by setting a variable in the model level variable table. Enter a variable in the table called EXTR_MODEL and set its value to the name of the transistor whose parameters are being extracted. When the extraction transforms are executed, IC-CAP refers to the correct Parameters table entry as it writes the extracted value back to the table. For example, to use a function list transform on the model NPN1 mentioned above, add the following to the model level variable table:

EXTR_MODEL NPN1

Each time another transistor is used for an extraction, place its name in the value field. A more efficient method of extracting individual transistor models is to create an individual setup for each device. The variable table at the setup level can then include the EXTR_MODEL entry, keeping the transistor extraction local to that setup. This can also be done in an analogous way at the DUT level.

It is sometimes necessary to specify the particular DUT in a circuit that should be used in an extraction routine. For example, in a circuit that contains two MOSFETs there are two different sets of geometry parameters (L and W). For the extraction to work correctly, the EXTR_DUT variable must be set to the name of the transistor with the correct geometry parameters. Therefore, to characterize transistor M1, which uses model NMOS1, add the following to the model level variable table:

EXTR_DUT M1
EXTR_MODEL NMOS1

Situations where EXTR_DUT must be set can also arise when test circuits are defined. In this case, DUT parameters that normally appear without a prefix in the DUT Parameters table will include the transistor name from the Test Circuit as a prefix. For the extractions to use these parameters, EXTR_DUT must be set to the transistor name that is used in the test circuit.

Extracting Parameters Through Optimization

It is not always possible to adequately isolate a circuit component before using a standard extraction function. In these cases it is still possible to extract model parameters by using the optimize function. As with any extraction function, successful use of the optimizer requires that the parameters being optimized have a dominant effect over the simulation of the measured characteristics. Refer to Optimizing, for more information regarding optimization.

In the OR/NOR gate shown in ECL OR/NOR Schematic Diagram, it is possible to use the optimizer to extract the values of NPN1.IS, NPN1.NF, NPN1.BF and RIEE. The following sequence of operations describes how to accomplish this.

  1. Make an Ic and Ib versus V measurement between the NOR, IN1 and VEE terminals.
    1. Connect the VEE, VREF and IN2 terminals to constant voltage sources of 0V. This keeps the base-emitter diodes of Q2 and Q0 in an off state. Disconnect VCC from the circuit.
    2. Connect the NOR terminal to a voltage of approximately 1.0V.
    3. Sweep the voltage on the IN1 terminal so that the measured currents at the NOR (collector) terminal are in the 1nA to 1μA range.
  2. Set up an optimization transform that optimizes the values of NPN1.IS, NPN1.NF, and NPN1.BF over the measured current. At low currents, RIEE has a minimal affect on the I-V relationship.
    • The target data is the measured Ic and Ib currents. The simulated data comes from the simulation of these currents.
    • The Parameters table contains NPN1.IS, NPN1.NF and NPN1.BF
  3. Change the sweep voltage on the IN1 terminal so that the measured current at the NOR terminal is in the 10μA to 1mA range.
    • The measured current should deviate from an exponential function due to the debiasing effect from RIEE.
  4. Set up an optimization transform that optimizes the value of RIEE over the measured current.
    • The target data is the measured Ic current. The simulated data comes from the simulation of this current.
    • The Parameters table contains only the circuit element RIEE.

After each of these measurements and optimizations has been executed, the Model Parameters table is updated with the extracted values of these elements.

Circuit Simulation

Circuit simulation is performed identically to single device simulation. The circuit usually has more inputs and outputs defined than a single device. In addition, the simulated circuit can use independent or controlled voltage and current sources that are defined within the Circuit Editor. When IC-CAP simulates a circuit, it first builds a complete SPICE deck from the circuit description and the setup table. The source names are built from the source type (V or I) and the nodes to which they are connected. Use of the simulation debugger can improve efficiency in performing successful simulations. Knowledge of how IC-CAP interacts with the SPICE simulators gives you more control over the options available for circuit simulation. For more information, refer to SPICE Simulators.

One of the advantages of simulating circuits through IC-CAP is the increased levels of analysis available. IC-CAP allows a sweep of more parameters than with a stand-alone SPICE simulator. For example, it is possible to simulate a circuit's behavior over bias conditions, component values and temperature in the same simulation. Once a simulation is complete, you may further analyze the stimulus and response data with IC-CAP's numerical and graphic capabilities. The two-port simulation features enable you to study the high-frequency characteristics of a circuit using any of the S, H, Y, or Z 2-port parameters.

Design Optimization

Designing a circuit usually follows a path of defining a block level functional description, translating it into discrete circuit components, then optimizing those components for the required performance. This last stage can be simplified with the IC-CAP system. It is possible to specify the desired performance from a circuit and then let the IC-CAP optimizer find the best component and model parameters to satisfy it. The following is an overview of how to do this.

  1. Enter a circuit with a first order estimate of the required parameters and component values.
  2. Create a setup with the inputs and outputs that simulate the desired region of performance.
  3. Simulate the circuit to create a set(s) of output data.
  4. Copy the simulated data into the measured data set(s) in the outputs.
    1. Type the letter S in the Type field and press Return.
    2. Type the letter B in the same field to replace the letter S.
  5. Save the desired outputs to files using the Write to File menu choice on each output.
  6. Edit the files using any editor. Scan down the file to find the type MEAS data section. This is where the measured data begins. Edit the output values, replacing them with the desired performance values for the circuit. Save the file when done.
  7. Read the file (and thus the new data) back into the outputs in IC-CAP using the Read from file command on the desired outputs.
  8. Set up an optimization transform to find the required parameter and component values that best match the new measured data.

This type of design optimization can save many hours of iteration in fine-tuning high-performance circuit designs.

Test Circuits

When measuring a single device or a complex circuit you often require additional components for biasing, setting operating points, or tuning the high-frequency performance characteristics. Even when no additional components are required, there may still be some parasitic elements introduced by the connections of the device to the instrumentation. Examples of this are DC resistance in probe-to-wafer contacts, inductances in IC package bond wires, and the shunt resistances in the bias ports of network analyzers. The Test Circuit in IC-CAP allows you to include these elements when performing a simulation or optimization without including them in the main circuit description or device model.

Syntax

A circuit editor is available for each DUT. To access it, select Edit in the DUT Circuit folder. This produces a window that has both the DUT Parameters table and the test circuit editor. The mechanics of using this editor are the same as using the circuit editor.

The test circuit adds another level of circuit hierarchy to the overall system being measured and modeled. It is implemented through a circuit description that uses the SPICE subcircuit syntax. The example test circuit shown in the following figure adds a capacitor and resistor to the outputs of the ECL logic gate described earlier.

Test Circuit for an ECL Logic Gate

This test circuit is added to the SPICE circuit deck each time a simulation is called or when an optimization that uses a SPICE simulation is performed. It does not modify the original model description in any way. The values of the elements in the test circuit can be modified in the DUT Model Parameters.

Hierarchical Modeling

The previous test circuit section on illustrated one way to include hierarchy in an overall circuit description. The test circuit, however, is at the highest level of hierarchy in an IC-CAP circuit. It is also possible to build a complete circuit by combining smaller circuit or transistor models into one subcircuit definition. This way, you can update the models of smaller subcircuits or individual components and have these changes automatically propagate into all circuits that use it.

Circuits Built from Sub-models

The ECL logic gate defined in ECL OR/NOR Schematic Diagram uses two sizes of NPN transistors. Each transistor has a separate .MODEL card associated with it. These transistor model definitions can be removed from the logic gate circuit and reference other models currently active in IC-CAP. When a simulation is performed, IC-CAP includes these device models in the circuit definition.

To use external models, the models that you want to include must be in the IC-CAP model list. In the circuit definition that uses these model references, remove the .MODEL card. The model name used for the transistors should then be the same as the names in the IC-CAP model list. To use this technique for the ECL logic gate, read in models for the NPN1 and NPN2 transistors into IC-CAP. Then delete the two model cards in the logic gate circuit. The resulting model list and circuit description are shown in the following 2 figures.

This approach provides flexibility. It allows you to keep a standard library of device models to include in larger circuits requiring accurate device models. This allows you to quickly cut-and-paste different component models into circuits and compare performance. It also greatly reduces the size of the circuit definition that needs to be maintained.

Model List Window for Hierarchical Circuit Definition

Hierarchical Circuit Description for ECL OR/NOR Logic Gate

Functional Circuit Blocks

Previous sections in this topic provided different aspects of the use of IC-CAP for modeling complete functional circuits. This section provides detailed examples of circuit models and custom model extractions you can create. These examples are provided to stimulate ideas for using IC-CAP to meet specific circuit modeling requirements.

Types of Circuits in IC-CAP

The types of circuits for measurement and simulation with IC-CAP are unlimited. Anything that can be simulated on a stand-alone SPICE simulator can be simulated with IC-CAP. In fact, any type of system that can be measured with the IC-CAP library of instruments can be characterized.

With the variety of components supported by SPICE, IC-CAP can be used to both characterize and design circuit modules. Classical examples of both single device and functional circuit modeling problems that are easily solved with IC-CAP are included.

Modeling the Reverse Active Region of an NPN Transistor

One of the constant sources of error in modeling the performance of a reverse active NPN transistor is the parasitic PNP formed by the base, collector, and substrate of the integrated structure. (This was briefly described in PNP Transistors) A simple solution to modeling this region of operation is to use the complete functional circuit displayed in the following figure.

NPN Transistor with Parasitic PNP

Model file npnwpnp.mdl is included as an example of solving this problem. It has a single DUT/Setup that measure and model the reverse active operation of an NPN transistor.

The previous figure shows that the emitter of the PNP steals current from the base terminal of the NPN. The single dominant parameter that models this PNP current flow is the saturation current IS. (Modeling the transistor at this point assumes that the DC NPN parameters have already been obtained using another model file. The bjt_npn.mdl model file has a complete set of DUTs and setups to perform this. For more information, refer to Bipolar Transistor Characterization.)

The rgummel setup then uses an optimize function to simultaneously extract the reverse active NPN parameters BR, IKR, ISC, and NC and the PNP parameter IS. The optimization proceeds by simulating the compound device, which is represented as a 2-transistor circuit, and numerically adjusting these model parameters.

The plot in the following figure is of reverse beta versus emitter current. It includes the simulation of the single transistor reverse model and measurement and simulation of the 2-transistor compound structure. The result of this extraction is a near perfect agreement between measured and simulated data. Also examine the resulting magnitudes of both IS (large enough to not be negligible) and BR (much higher than for a single device extraction). This example shows the improvement you can attain in using a full circuit description to model an integrated device structure.

Reverse Beta versus Ie for Single NPN and Compound NPN-PNP Structure

Modeling an Operational Amplifier

The operational amplifier is included with IC-CAP as an example of how to do relatively complex macro modeling. It illustrates the simplification of a complex circuit to the necessary and sufficient components that enable it to be accurately represented. This model includes a Program transform that extracts model parameters from data sheet specifications of its performance. The inputs to this transform could also be measurements of the opamp's electrical characteristics. This same Program transform has also been converted into a standard IC-CAP function by writing it in the C programming language (in the userc.c module) and compiling and linking it into the system. The circuit chosen follows the model developed by Boyle, Cohn, Pederson, and Solomon [1]. This circuit model is in the opamp.mdl example file.

Opamp Macro Model

The stages in this opamp model are: non-linear differential input, intermediate linear gain, and output driver. These enable most of the possible operating regions of the complete circuit to be adequately simulated.

The input stage contains transistors Q1 and Q2 connected as a differential amplifier, biased with a fixed current source (see figure above). Q1 and Q2 provide both differential mode (DM) and common mode (CM) characteristics. Passive components in the input stage provide slew rate effects (C2, Ce, Re1, Re2), 0dB frequency control (Rc1, Rc2), DM excess phase (C1), and CM input resistance (R1).

The intermediate gain stage provides linear amplification through voltage controlled current sources Ga, and Gb, which model the differential gain of the opamp. Capacitor C2 controls the dominant pole. CM gain is modeled with the voltage controlled source that has the coefficient Gcm.

In the output stage, AC and DC output resistances are modeled with Ro1 and Ro2. Output drive voltage is supplied through diodes D1 and D2 and voltage controlled voltage source (Gc*v6*Rc). The independent voltage sources in series with diodes D3 and D4 clamp the opamp under conditions that would force the output voltage to one of the supply rails.

The development of this opamp model uses the concepts of simplification and buildup to reduce the number of active and passive components. For example, to maintain non-linear effects the input stage has been simplified to two transistors, and an independent current source has been substituted for the usual bias circuitry. In the interstage amplifier, buildup is used to emulate a circuit characteristic through alternate circuitry. The stage is modeled by two voltage controlled current sources and a capacitor for compensation. These techniques take a piece-by-piece approach to the development of a model. They can be applied to virtually any circuit or subcell.

Opamp Circuit Model

The following figure shows the macro model that represents the full opamp circuit, followed by circuit elements in order from the input to the output stage. Opamp Circuit Diagram shows the complete opamp model circuit definition used in this example.

Opamp Circuit Definition
Opamp Circuit Diagram

Inputs to the Opamp Macro Extraction

Inputs to the opamp model extraction describe its electrical performance. These characteristics can be measured on actual devices or obtained from data sheet specifications. Due to the flexibility of the origin of the inputs, you can experiment with the opamp's performance as it relates to the model elements that control it. The following table lists the inputs to the opamp extraction.

opamp Extraction Inputs

Input Name

Contents

Slew Rate +

positive-going slew rate

Slew Rate-

negative-going slew rate

Bias Current

average input base bias current

Bias Offset

input bias offset current

Volt Offset

input offset voltage

Av(DM)

open loop differential mode voltage gain

BW

unity gain bandwidth (Av(DM) * f(-3dB))

Excess Phase

excess phase at f(0dB) due to 2nd pole

CMRR (dB)

common mode rejection ratio

Rout

low-frequency output resistance

Rout-ac

high-frequency output resistance

Isc+

positive short circuit current

Isc-

negative short circuit current

Vout_max+

positive output voltage where opamp clamps Iout

Vout_min-

negative output voltage where opamp clamps Iout

Power Diss

quiescent state power dissipation

Vcc supply

positive supply voltage

Vee supply

negative supply voltage

Nom. Q.IS

nominal transistor and diode saturation current

R2

differential gain setting resistor

Comp. Cap.

compensation capacitance

Temp.(C)

temperature for macro extraction and input specification

Inputs PNP?

flag to switch the inputs to PNP transistors

Debug?

flag to turn on debug output during extraction

Extraction Equations for the Opamp Macro Model

The inputs to the macro model extraction described are used by the set of equations shown in the following figure to produce the model parameters. These equations are programmed into the userc.c module exactly as shown.

Because of the simplicity of the equations, they can also be entered into a Program transform using the Parameter Extraction Language. This allows experimentation with model extraction techniques before coding the final extraction in C and linking it to IC-CAP. This has been done with the opamp macro model to provide a typical example of writing custom model extractions.

C Coded Opamp Extraction Equations

Bias Circuitry

The opamp model, fully defined and model parameters extracted, can now be used as a functional circuit block. This requires that the opamp be biased with external supply voltages and circuit configuring components. This was demonstrated previously through the use of a test circuit. The test circuit implemented forms an inverting amplifier using an input and feedback resistor with the opamp. This results in a complete functional circuit whose performance can be studied in more detail. The test circuit definition and the resulting equivalent circuit are shown in the following 2 figures.

Test Circuit Definition to Form an Inverting Amplifier
Equivalent Schematic of Opamp in Inverting Amplifier

The plot in the following figure illustrates how this functional circuit can be studied. The opamp circuit has been simulated with the compensation capacitance used as one of the sweep parameters. The AC voltage gain is plotted versus frequency with steps of different values of C2. The diagonal line is the break point between process limitations and circuit limitations. To increase frequency response, the internal capacitor on the chip (nominal 30pF) would have to be reduced. To force earlier roll-off, more external capacitance can be added. This analysis indicates the range of gain-bandwidth product available for different values of capacitance. Similar analyses can be performed for any area of this circuit's operation.

AC Opamp Response vs C2 Capacitance

References

  1. G.R. Boyle, B.M. Cohn, D.O.Pederson, J.E. Solomon. Macromodeling of Integrated Circuit Operational Amplifiers, IEEE Journal of Solid-State Circuits, Vol. SC-9, No. 6, December 1974.