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Agilent Technologies


Curtice3_Model (Curtice-Cubic GaAsFET Model)


Available in ADS and RFDE

Supported via model include file in RFDE


Model parameters must be specified in SI units.

Name Description Units Default
NFET N-channel model type: yes or no None yes
PFET P-channel model type: yes or no None no
Idsmod Ids model: 1=CQ 2=CC 3=Statz 4=Materka 5=Tajima 6=symbolic 7=TOM 8=Modified Materka None 2
Beta2 Coefficient for pinch-off change with respect to Vds 1/V 0.0
Rds0 ††† DC D-S resistance at Vgs=0 Ohm 0
Vout0 output voltage (Vds) at which A0, A1, A2, A3 were evaluated V 0
Vdsdc Vds at Rds0 measured bias V 0
Tau transit time under gate sec 0.0
Gamma current saturation 1/V 2.0
Tnom nominal ambient temperature at which these model parameters were derived °C 25
Idstc Ids temperature coefficient None 0
A0 , †† cubic polynomial Ids equation coefficient 1 A 0
A1 , †† cubic polynomial Ids equation coefficient 2 A/V 0
A2 , †† cubic polynomial Ids equation coefficient 3 A/V 2 0
A3 , †† cubic polynomial Ids equation coefficient 4 A/V 3 0
Vtotc VTO temperature coefficient V/°C 0.0
Betatce BETA Exponential Temperature Coefficient %/°C 0.0
Rin ††† channel resistance Ohm 0.0
Rf ††† gate-source effective forward-bias resistance Ohm infinity
Fc forward-bias depletion capacitance coefficient (diode model) None 0.5
Gscap 0=none, 1=linear, 2=junction, 3=Statz charge, 5=Statz cap None linear
Cgs †† zero-bias gate-source capacitance F 0.0
Cgd †† zero-bias gate-drain capacitance F 0.0
Rgd ††† gate drain resistance Ohm 0.0
Gdcap 0=none, 1=linear, 2=junction, 3=Statz charge, 5=Statz cap None linear
Rd †† drain ohmic resistance Ohm fixed at 0
Rg gate resistance Ohm fixed at 0
Rs ††† source ohmic resistance Ohm fixed at 0
Ld drain inductance H fixed at 0.0
Lg gate inductance H fixed at 0.0
Ls source inductance H fixed at 0.0
Cds †† drain-source capacitance F 0.0
Crf †† with Rds, models frequency dependent output conductance F 0.0
Rds ††† additional output resistance for RF operation Ohm 0.0
Gsfwd 0=none, 1=linear, 2=diode None linear
Gsrev 0=none, 1=linear, 2=diode None None
Gdfwd 0=none, 1=linear, 2=diode None None
Gdrev 0=none, 1=linear, 2=diode None linear
R1 ††† approximate breakdown resistance Ohm infinity
R2 ††† resistance relating breakdown voltage to channel current Ohm fixed at infinity
Vbi built-in gate potential V 0.85
Vbr gate-drain junction reverse bias breakdown voltage (gate- source junction reverse bias breakdown voltage with Vds  <    0) V 1e100
Vjr breakdown junction potential   0.025
Is † †† gate junction saturation current (diode model) A 1.0e-14
Ir gate reverse saturation current A 1.0e-14
Xti Saturation Current Temperature Exponent None 3.0
Eg energy gap for temperature effect on Is None 1.11
N gate junction emission coefficient (diode model) None 1
A5 time delay proportionality constant for Vds None fixed at 0.0
Imax explosion current A 1.6
Imelt explosion current similar to Imax; defaults to Imax (refer to Note 3) A defaults to Imax
Taumdl Use 2nd order Bessel polynomial to model tau effect in transient: yes or no None no
Fnc flicker noise corner frequency Hz 0.0
R gate noise coefficient None 0.5
P drain noise coefficient None 1.0
C gate-drain noise correlation coefficient None 0.9
Vto (not used in this model) None None
wVgfwd gate junction forward bias (warning) V None
wBvgs gate-source reverse breakdown voltage (warning) V None
wBvgd gate-drain reverse breakdown voltage (warning) V None
wBvds drain-source breakdown voltage (warning) V None
wIdsmax maximum drain-source current (warning) A None
wPmax maximum power dissipation (warning) W None
Kf flicker noise coefficient None 0.0
Af flicker noise exponent None 1.0
Ffe flicker noise frequency exponent None 1.0
AllParams DataAccessComponent for file-based model parameter values None None
Parameter value varies with temperature based on model Tnom and device Temp. †† Parameter value scales with Area. ††† Parameter value scales inversely with Area. A value of 0.0 is interpreted as infinity.

  1. This model supplies values for a GaAsFET device.
  2. The Curtice cubic model is based on the work of Curtice and Ettenberg. Curtice3_Model contains most of the features described in Curtice's original paper plus some additional features that may be turned off. The following subsections review the highlights of the model. Refer to Curtice's paper [1] for more information.
  3. Imax and Imelt Parameters
    Imax and Imelt specify the P-N junction explosion current. Imax and Imelt can be specified in the device model or in the Options component; the device model value takes precedence over the Options value.
    If the Imelt value is less than the Imax value, the Imelt value is increased to the Imax value.
    If Imelt is specified (in the model or in Options) junction explosion current = Imelt; otherwise, if Imax is specified (in the model or in Options) junction explosion current = Imax; otherwise, junction explosion current = model Imelt default value (which is the same as the model Imax default value).
  4. Use AllParams with a DataAccessComponent to specify file-based parameters (refer to "DataAccessComponent" in Introduction to Circuit Components). A nonlinear device model parameter value that is explicitly specified will override the value set by an AllParams association.


Drain-Source Current

Drain current in Curtice3_Model is calculated with the following expression:

Ids = Idso × tanh(Gamma×Vds), TauNEW = Tau + A5 × Vds


Idso = [A0 + A1 × V1 + A2 × V12 + A3 × V13 ] + (Vds − Vdsdc)/Rds0
V1 = Vgs(t - TauNEW) × (1 + Beta2 × (Vout0 - Vds)), when Vds ≥ 0.0 V
V1 = Vgd(t - TauNEW) × (1 + Beta2 × (Vout0 + Vds)), when Vds < 0.0 V

The latter results in a symmetrical drain-source current that is continuous at Vds=0.0 V. For values of V1 below the internal calculated maximum pinchoff voltage Vpmax, which is the voltage at the local minimum of the function:

A0 + A1 × n + A2 × n2 + A3 × n3

Idso is replaced with the following expression:

Idso = [A0 + A1 × Vpmax + A2 × Vpmax2 + A3 × Vpmax3] + (Vds − Vdsdc)/Rds0

If the Idso value is negative (for Vds > 0.0V), current is set to 0.
This implementation models the delay as an ideal time delay.


When Rds0 is defaulted to 0, the term (Vds − Vdsdc)/Rds0 is simply ignored and there is no divide by zero.

Junction Charge (Capacitance)

Two options are provided for modeling the junction capacitance of a device: to model the junction as a linear component (a constant capacitance); to model the junction using a diode depletion capacitance model. If a non-zero value of Cgs is specified and Gscap is set to 1 (linear), the gate-source junction will be modeled as a linear component. Similarly, specifying a non-zero value for Cgd and Gdcap=1 result in a linear gate-drain model. A non-zero value for either Cgs or Cgd together with Gscap=2 (junction) or Gdcap=2 will force the use of the diode depletion capacitance model for that particular junction. Note that each junction is modeled independent of the other; therefore, it is possible to model one junction as a linear component while the other is treated nonlinearly. The junction depletion charge and capacitance equations are summarized next.

Gate-Source Junction

For Vgc < Fc × Vbi

For Vgc ≥ Fc × Vbi


Gate-Drain Junction

For Vgd < Fc × Vbi

For Vgd ≥ Fc × Vbi


Gate Forward Conduction and Breakdown

Agilent's implementation of the Curtice quadratic model provides a few options for modeling gate conduction current between the gate-source and gate-drain junctions. The simplest model is that proposed by Curtice for his cubic polynomial model (see Curtice3). This model assumes an effective value of forward bias resistance Rf and an approximate breakdown resistance R1. With model parameters Gsfwd = 1 (linear) and Rf reset to non-zero, gate-source forward conduction current is given by:
Igs = (Vgs - Vbi)/Rf when Vgs > Vbi

= 0 when Vgs ≤ Vbi.

If Gsfwd = 2 (diode), the preceding expression for Igs is replaced with the following diode expression:

Similarly, with parameter Gdfwd = 1 (linear) and Rf set to non-zero, gate-drain forward conduction current is given by:
Igd = (Vgd - Vbi)/Rf when Vgd > Vbi

= 0 when Vgd ≤ Vbi.

If Gdfwd is set to 2 (diode), the preceding expression for Igd is replaced with a diode expression:

The reverse breakdown current (Idg) is given by the following expression if R1 is set non-zero and Gdrev = 1 (linear):

Igd = Vdg - Vb)/R1 when Vdg ≥ Vb and Vb > 0

= 0 when Vdg < Vb or Vb ≤ 0

Vb = Vbr + R2 × Ids
If Gdrev is set to 2, the preceding Igd expression is replaced with a diode expression:

With Gsrev -= 1 (linear) and R1 set to non-zero, the gate-source reverse breakdown current Igs is given by the following expression:

Igs = (Vsg - Vb)/R1 when Vsg≥ Vbi and Vb > 0

= 0 when Vsg ≤ Vbi or Vb ≤ 0

If Gsrev is set to 2, the preceding Igs expression is replaced with a diode expression.

When the diode equations are both enabled, the DC model is symmetric with respect to the drain and source terminals. The AC model will also be symmetric if, in addition to the latter, Cgs=Cgd.

High-Frequency Output Conductance

Curtice3_Model provides the user with two methods of modeling the high frequency output conductance. The series-RC network dispersion model (Curtice Cubic Model) is comprised of the parameters Crf and Rds and is included to provide a correction to the AC output conductance at a specific bias condition. At a frequency high enough such that Crf is an effective short, the output conductance of the device can be increased by the factor 1/Rds. (Also see [2]).

Curtice Cubic Model

Temperature Scaling

The model specifies Tnom, the nominal temperature at which the model parameters were calculated or extracted. To simulate the device at temperatures other than Tnom, several model parameters must be scaled with temperature. The temperature at which the device is simulated is specified by the device item Temp parameter. (Temperatures in the following equations are in Kelvin.)
The saturation current Is scales as:

The gate depletion capacitances Cgso and Cgdo vary as:

where y is a function of junction potential and energy gap variation with temperature.
The gate junction potential Vbi varies as:

where ni is the intrinsic carrier concentration for silicon, calculated at the appropriate temperature.
The cubic polynomial coefficients A0, A1, A2, and A3 vary as:

If Betatc = 0 and Idstc ≠ 0
IdsNEW = Ids × (1 + Idstc × (Temp − Tnom))

Noise Model

Thermal noise generated by resistors Rg, Rs and Rd is characterized by the spectral density:

Parameters P, R, and C model drain and gate noise sources.

For Series IV compatibility, set P=2/3, R=0, C=0, and Fnc=0; copy Kf, Af, and Ffe from the Series IV model.

Calculation of Vto Parameter

The Vto parameter is not used in this model. Instead, it is calculated internally to avoid the discontinuous or non-physical characteristic in ids versus vgs if A0, A1, A2, A3 are not properly extracted.
For a given set of As, ADS will try to find the maximum cutoff voltage (Vpmax), which satisfies the following conditions:

f(Vpmax) = A0 + A1 × Vpmax + A2 × Vpmax2 × 2 + A3 × Vpmax3 × 3 ≤ 0
first derivative of f(Vpmax) = 0 (inflection point)
second derivative of f(Vpmax) > 0 (this is a minimum)

If Vpmax cannot be found, a warning message is given cubic model does not pinch off .
During analysis, the following are calculated:

vc = vgs × (1 + Beta2 × (Vout0 - vds))
ids = ((A0 + A1 × vc + A2 × vc×2 + A3 × vc×3) + (vds − Vdsdc) / Rds0)
   × tanh(Gamma × vds)

If ids < 0 then sets ids = 0.

If ids > 0 and Vc ≤ Vpmax then calculates ivc as follows:

ivc = (f(Vpmax) + (vds - Vdsdc) / Rds0) × tanh(Gamma × vds)
If ivc > 0 then sets ids = ivc and gives a warning message Curtice cubic model does not pinch off, Ids truncated at minimum.

else set ids = 0

To ensure the model is physical and continuous, it is important to obtain a meaningful set of As that Vpmax can be found.

  1. W. R. Curtice and M. Ettenberg, "A nonlinear GaAsFET model for use in the design of output circuits for power amplifiers," IEEE Trans of Microwave Theory Tech , vol. MTT-33, pp. 1383-1394, Dec. 1985.
  2. C. Camacho-Penalosa and C.S. Aitchison, "Modelling frequency dependence of output impedance of a microwave MESFET at low frequencies," Electron. Lett., Vol. 21, pp. 528-529, June 6, 1985.
  3. P. Antognetti and G. Massobrio, Semiconductor device modeling with SPICE, New York: McGraw-Hill, Second Edition 1993.
  4. A. Cappy, "Noise Modeling and Measurement Techniques," IEEE Transactions on Microwave Theory and Techniques , Vol. 36, No. 1, pp. 1-10, Jan. 1988.